Particle size : 5nm~40nm
Application : CMP Process for Semiconductor manufacturing.
Features
① The amount of abrasion can be adjusted depending on the particle size.
② For the Advanced Device process, the shape should be uniform and the particle size distribution variation should be small.
③ High selection ratio for silicon nitride and Poly-Si film.
④ Minimization of defects. (such as scratches and dishing)
In the domestic semiconductor manufacturing process, calcined ceria based polishing is currently used and the ceria nano particles used are exclusively supplied by Solvay chemical.
The market is demanding a shift from Calcinated materials to Colloidal materials as the importance of Scratch and Defect increases due to the complexity and high-rise of semiconductor structures.
We are localizing Ceria materials and developing next-generation materials using underwater plasma synthesis method.
As the semiconductor becomes densely packed, high-rise, multi-layered, and with finer pitches, Scratch, Protect prevention, and fine pitch response are required. A 5nm-class ceria is developed for this demands.
We synthesizes colloidal ceria particles with a size of several nm, a next-generation ceria material.
The 5nm ceria with underwater plasma synthesis can prevent scratching and dishing of the wafer and is excellent for the re-touch step at the end of the CMP process.
